A common requirement of current integrated circuit manufacturing and packaging is the use of interposers to receive single or multiple integrated circuit dies. The use of through vias or through silicon vias (“TSVs”) extending through the interposers is increasing. These through vias allow electrical coupling between integrated circuit dies and components mounted on one side of an interposer, and terminals such as solder balls mounted on the opposite side of the interposer. Further, the use of TSV technologies with silicon interposer substrates enable wafer level processing (“WLP”) of the interposer assemblies. This technique is increasingly applicable to increasing memory or storage device density, for example, without added circuit board area. As demand for hand held and portable devices such as smart phones and tablet computers increases, board area and board size restrictions also increases, and the use of the interposer assemblies and TSVs can meet these requirements. These techniques apply to semiconductor wafers such as silicon wafers, but may also apply to other interposer materials, for example BT resin and other interposer materials, where through via connections, conductive patterning for connecting components, and component mounting may be performed.
During processing of the dies mounted on the wafer interposer, which may be referred to as a “die on wafer” (“DOW”) assembly, a molding step may be performed to form a mold compound surrounding the individual integrated circuit die components. The mold compound may be partially removed from the top of the die side to expose the upper surface of the integrated circuit dies.
Using conventional plastic mold compound on the dies in a conventional compression molding process on the silicon wafer interposer results in some wafer warp. This warp can become even greater when the wafer is then subsequently thinned to complete the TSVs. The molding is performed to surround the ICs with the plastic mold compound, and then the silicon wafer is thinned in a backgrinding operation to expose the opposite end of the TSVs. Because the semiconductor wafer interposer is now very thin, the wafer warp already present after molding can increase greatly after the wafer thinning operation. Subsequent wafer process steps that rely on a planar exterior surface of the assembly, such as vacuum tools used for pick and place in the solder ball bumping process, cannot work reliably on the warped wafer interposers. This reduces yield and can result in the waste of the mounted integrated circuit dies, which are known good dies (“KGDs”), and loss of the KGDs greatly increases costs. Rework or manual intervention into the processing may be required when automated processes cannot handle the warped wafer interposers.
A continuing need thus exists for methods and systems to efficiently perform molding for DOW interposer assemblies without the warp and the attendant problems experienced when using the known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.